Dynomotion

Group: DynoMotion Message: 10964 From: Hardy Family Date: 1/30/2015
Subject: Request multiplexing step/dir signals for axes 4,5
For the controller motherboard we are designing, it would be highly preferable to mount the Kflop directly on the board (using socket headers rather than stub ribbon cables).  We will need to route cut-outs for the USB and RJ45 connectors since the Kflop will be "upside down" on the motherboard and those connectors are fairly tall.

Unfortunately, since this is a 6-axis machine, we would still have to make a wired connection to the RJ45 jack (JP5) to access the step/dir signals for axes 4 and 5.  What we would much prefer is to be able to have a bit that the FPGA would use to route these signals to JP7 pins 7-10 (similar to the existing bit which moves JP7 axes to JP4,6).  Actually, it doesn't matter which pins are used (JP7,4 or 6), but since we don't use encoders, those JP7 pins would not make us unhappy :-)

This would leave the RJ45 free for further expansion of the controller.

So I guess the question is, would it be possible for Dynomotion to tweak the FPGA config to add this feature?

Regards,
AB
Group: DynoMotion Message: 10981 From: Tom Kerekes Date: 2/2/2015
Subject: Re: Request multiplexing step/dir signals for axes 4,5
Hi AB,

Multiplexing I/O pins consumes quite a bit of FPGA resources (that we don't have).  It also adds complexity and confusion to the options we already have.

If using the other connector is a major issue we might consider doing it for an NRE charge.  But it would be expensive and then would require custom code, testing, etc. for your application.

Regards
TK

Group: DynoMotion Message: 10985 From: Hardy Family Date: 2/2/2015
Subject: Re: Request multiplexing step/dir signals for axes 4,5
No problem.  We'll think about it.

I don't think we would have a problem with NRE, in which case we would not need the muxing, just change the UCF to swap the FPGA pins.  Provided we could have a build system to link in the custom FPGA config, then we could take that task off your hands, so you wouldn't have to change your manufacture process.

Anyway, we'll contact you directly if we need to do this.

Regards,
AB


On Mon, Feb 2, 2015 at 9:14 AM, Tom Kerekes tk@... [DynoMotion] <DynoMotion@yahoogroups.com> wrote:
 

Hi AB,

Multiplexing I/O pins consumes quite a bit of FPGA resources (that we don't have).  It also adds complexity and confusion to the options we already have.

If using the other connector is a major issue we might consider doing it for an NRE charge.  But it would be expensive and then would require custom code, testing, etc. for your application.

Regards
TK